Microfabrication Facilities at the SMC

This equipment and the research staff are located in the Scottish Microelectronics Centre (SMC), a purpose built facility at the University's Science and Engineering campus at King's Buildings. The complex consists of approximately 250m2of class 10and 100m2of class 100 cleanrooms  and 1000m2of office and laboratory space.   It is a 200mm capable facility with the flexibility for processing smaller wafer sizes as well as chips and the SMC hosts both academic and industrial research operations.  The facility focusses on smart microsystems technology and integration and has a long track record of postprocess CMOS wafers (More than Moore technology).  Contact details to arrange access and/or processing services are detailed on this page.

Environment

The cleanrooms are located in the purpose build £4.2M Scottish Microelectronics Centre building. This class 10 facility comprises 250 sq metres is controlled to 21±1°C with a relative humidity of 40±5% with a raised floor being used as the air return to the plenum.  Each bay is serviced with DI, town and chilled water, nitrogen, compressed air, power, gases and vacuum.

Wafer Fabrication Equipment

The Laboratories maintains the following major items of processing equipment:

  • DC Magnetron Sputter Coater - Balzers BAS450 coater system with two 5 in × 10 inch targets presently used for coating up to 24 × 3 inch wafer with Al/1%Si, Al,W and Ti. It is also capable of coating 4 and 6 inch wafers. Ion beam pre-cleaning is available using an Ion Tec Inc Kafmann source.
    Oxford Plasmalab System - 400 magnetron sputtering system capable of sputtering Al/1%Si, Al, W, Ta, Ti and TiN on 6 and 8 inch wafers. Ion beam pre-cleaning is also available.
  • Diffusion Furnace Tubes - Three quad stack Tempress Omega L furnaces, upgraded to direct digital control with supervisor computer. The systems are tooled for 3 inch wafers and support the following processes:200mm tubes are available for oxidation, LPCVD silicon nitride (inc low stress) and polysilicon (inc low stress)
    • Dry oxidation (with HCl gettering)
    • Wet oxidation (burnt hydrogen with HCl gettering)
    • Nitrogen anneals (6" available)
    • Phosphorus deposition (solid source or POCl3)
    • LPCVD of Polysilicon
    • LPCVD of Silicon Nitride
  • Dielectric Deposition
    • Oxford Plasma Technology ECR deposition of SiO2 and Nitride(3-6 inch wafers)
    • STS Miultiplex PECVD vacuum load-lock system configured for SiOx and low stress nitride. Capable of coating up to 8" wafers.
  • Dry Etching
    • STS PF 508 barrel reactor for plasma ashing of photoresist from up to 150 wafers/run. (3-8 inch wafers).
    • STS Multiplex load locked aluminium and polysilicon RIE etcher using SiCl4, and Cl2 chemistry (3-6 inch wafers). 
    • Plasmatherm Versaline DSE IV deep Si etch system (3-8 inch wafers).
    • STS Multiplex ICP - Load locked inductively coupled plasma etch system configured for deep Si etching. Capable of etching up to 8" wafers
  • Chemical Mechanical Polishing (CMP)
    • Presi Mecapol E460 polisher configured for 3-8 inch wafers
    • SVG 8600 series double sided 6 inch scrubber
  • Wet Etching - Fume extracted class 10 laminar flow chemical stations permit safe cleaning of furnace quartzware and the processing of 3 to 8 in wafers in industry standard cassettes through the stadard mineral acid cleaning and etching treatments.Wafers are finally dried in Fluoroware or Tempress rinser/driers. A Maragoni dryer is also available(3-8").
  • Wafer Lithography - Photoresist coating, developing and baking are achieved on 3" a SVG 8600 track system and a CEE 75-200mm coater/develop system each comprising:
    • Dehydration bake/ vapour prime, coat, hotplate softbake
    • Post exposure bake, spray/puddle develop, hotplate hardbake. Although facilities for negative resist processing are available, positive resist is the preferred patterning medium and the only one possible on the DSWs
    • Spray coating of photoresist is also available (EVG 101)

    Mask aligning and exposure are carried out using contact printing or DSW (reduction projection printing) as appropriate. DSW printing is preferred for those chips greater than 6 mm square or those including geometries less than 3 microns. The machines in use are:

    • Contact printer : Cobilt 2020 soft contact (3")
    • Projection printer (double sided) : Karl Suss MA8/B8, (3, 4, 6 & 8") with IR alignment
    • Wafer Stepper: Optimetrix 8605, g-line, 0.32 NA, (3, 4 & 6")
    • Wafer Stepper: Nikon Body 9, i-line, 0.57 NA, (6 & 8")

In-Line Inspection and Measurement

Wafers are subject to visual inspection at all stages in processing using a variety of metallurgical microscopes from various manufacturers including Leitz, Reichart-Jung, Olympus, Leica DM12000 (optical IR, UV and 3D mapping) etc

In addition, linewidth measurements on masks and wafers are made to ±0.2 microns using a Biorad Coincident Shear System. Completed devices and wafers may be subjected to SEM analysis using a Htachi 4500 or whole wafers on a Philips EE40FEG. Access to SEMs, FIB and an AFM is also available

Profiling of wafer topography is available using a Dektak Model 8000 surface profiler to record step height variations in the range 0.01 to 60 microns.

Refractive index and thickness of visually transparent dielectrics such as silicon dioxide and silicon nitride are measured using an Applied Materials Ellipsometer model AME500 and a Sopra SE-5 Spectroscopic ellipsometer. This method is particularly useful in the thickness range 0.005 to 0.2 microns. Thicker dielectric layers and polysilicon layers are more readily measured using the Nanoscope Model 010-180 reflectometer.

Sheet resistance of large area process layers is measured using a Veeco 1000 4 point probe.

Wafer mapping nanoindentation is available (Keysight G200)

Assembly

A low volume capability for the assembly of chips into Flat Packs, TO5 and Dual In-line packages is available using the following equipment:

  • Dicing Saw (DAD 640) - Disco 8" wafer chuck
  • Eutectic Die Attach - Dage-Precima Model EDB65 with mechanical scrub wetting
  • Wire Bond - Kulicke & Soffa Model 472 gold wire ultrasonic ball bonder
  • Disco 810 8" wafer grinder

Where devices may suffer degradation during eutectic die attach, low temperature processing is available using doped epoxy. Ultrasonic wire bonding provides the additional flexibility required for infrequent hybrid assembly jobs.

Off-Line Evaluation and Test

Parametric Testing

Two HP4062C test systems with 48 switchable pins are connected to a Karl Suss 200mm PA200 automatic wafer prober with ProbeShield® EMC for low signal  probing which can be used to perform measurements required by IC-CAP and other parameter extractors under software control. Similar measurements may also be made using HP4145, HP 4156 and Keithley 4200 semiconductor parameter analysers and CV measurements on other manual and semiautomatic probers.

Device and Process Simulation

The Facility uses workstations running with the UNIX operating system to give multi-user access to the Synopsis process and device simulation packages. The following programs are available:

  • TWB - Design of Experiments
  • SUPREM-3 - 1-D Process simulation
  • TSUPREM-4 - 1-D Process simulation
  • MEDICI - 1-D Process simulation
  • DAVINCI - 1-D Process simulation
  • AURORA - Parameter extraction
  • DEPICT - Photolithography
  • TERRAIN - Etch and Deposition
  • MICHELANGELO - Gridder and data display
  • LAYOUT Mask - definition
  • RAPHAEL - Capacitance/resistance calculations
  • ICCAP - Parameter extraction
  • RS/1 EXPLORE AND DISCOVERY - Design of Experiments
  • CORNERSTONE - DOE and Statistical Analysis

Address: 

Scottish Microelectronics Centre
School of Engineering and Electronics
Kings Buildings
University of Edinburgh
Edinburgh
EH9 3JF

Scottish Microelectronics Centre
Scottish Microelectronics Centre
DC Magnetron Sputter Coater
DC Magnetron Sputter Coater
Presi Mecapol E460 polisher
Presi Mecapol E460 polisher

Contact Name: 

Andrew Bunting (Commercial)
Anthony Walton (Academic)

Contact Email: