Chip gallery

Discover our Chip gallery.

Should you visit us in Edinburgh you will have the chance to appreciate our people and our labs, but also our creative side through an extensive display of “art-on-chips”. A few of these are illustrated below. Further information on each chip can be found in our PDF brochure.

  • ACNN1: Designers Designers: Sachin, Himadri, Mike, Alex. Purpose: Adiabatic neural network for ultra-low-power AI inference, option 1
  • ACNN2: Designers: Sachin, Himadri, Mike, Alex. Purpose: Adiabatic neural network for ultra-low- power AI inference, option 2
  • ACNN3: Designers: Sachin, Himadri, Mike, Alex. Purpose: Adiabatic neural network for ultra-low-power AI inference, option 3
  • Aggregator: Designers: Khaled, Yihan, Alex. Purpose: Analog-Domain aggregator circuit for RRAM-based neural network Accelerators
  • ASOCA1: Designers: Yihan, Shady, Alex. Purpose: RRAM Content addressable memory for symbolic AI processing, 1st generation
  • ASOCA2: Designers: Yihan, Yanjun, Alex. Purpose: A modular graph database accelerator
  • MELITA: Designers: FORTE design team (14 contributors). Purpose: Integrated characterisation platform for emerging RRAM technologies supporting up to 1 million DUTs
  • NeuroStripe 1.0: Designers: Xiongfei, Shiwei. Purpose: Bidirectional multi-chan- nel neural interface chip for closed-loop neuromodulation, version 1.0
  • PreSONIC: Designers: Grahame, Xiongfei, Shiwei. Purpose: A Scalable, Multi-Function, Integrated CMOS/Memristor Sensor Interface for Neural Sensing Applications
  • RADTEST: Designers: Ahmet, Alex, Themis. Purpose: Test structure for radiation hardened RRAM memory cells
  • SPIKA: Designers: Khaled, Yihan, Grahame, Alex. Purpose: An Energy-Efficient Time-Domain Hybrid CMOS-RRAM Compute-in-Memory Macro
  • TXL: Designers: Georgios, Shady, Ahmet, Themis. Purpose: Analogue content addressable memory macro for template matching at the edge

This article was published on